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CY24488
Quad PLL Clock Generator with Serial Interface (I2C)
Features
* Three output frequencies plus reference out * Programmable output frequencies via I2C serial interface * Output frequencies from 4.9152 to 148.5 MHz * Uses an external 27 MHz crystal or 27 MHz input clock * Optional analog VCXO * Programmable output drive strength to minimize EMI * The non-I2C equivalent is the CY22388 / 89 / 91 * 16-pin TSSOP package * 3.3V operation with 2.5V output buffer option
Benefits
* Meets most Digital Set Top Box, DVD Recorder, and DTV application requirements * Multiple high-performance PLLs allow synthesis of unrelated frequencies * Integration eliminates the need for external loop filter components * Complete VCXO solution with 120 ppm (typical pull range)
Block Diagram
CLKC PLL1 XIN/CLKIN VCXO XOUT VIN PLL3 PLL4 SCLK SDAT Serial Interface & Select Logic CLKG PLL2 Dividers & Multiplexers CLKD CLKE
Pin Configuration
XIN/CLKIN SCLK SDAT VIN
CLKF
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
XOUT AVDD DNC VDD2 VSS CLKG CLKF CLKE
VDD1 VSS CLKC CLKD
Table 1. Applications and Frequencies Output Clock CLKC Application Audio iLink HDMI CLKD Video USB Video-Pixel Freq. Modem iLink CLKE Video Ethernet PCI Processor CLKF CLKG see CLKC/D/E see CLKC/D/E Frequencies (MHz) 6.144, 8.192, 11.2896, 12.288, 16.384, 16.9344, 18.432, 22.5792, 24.576, 33.8688, 36.864 24.576 25.175, 28.322 27, 27.027, 54, 54.054, 81 12, 24, 48 74.25/1.001, 74.25, 148.5/1.001, 148.5 4.9152, 11.0592 24.576 13.5, 27, 54, 81, 108 25 33.3333, 66.6666 20, 30, 40, 50, 60, 80, 100 REFOUT or Copy of CLKC, CLKD or CLKE REFOUT or Copy of CLKC, CLKD or CLKE
Cypress Semiconductor Corporation Document #: 001-09608 Rev. *A
* 198 Champion Court
* San Jose, CA 95134-1709 * 408-943-2600 Revised October 31, 2006
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CY24488
Pin Description
Pin Name XIN/CLKIN XOUT CLKC CLKD CLKE CLKF CLKG SCLK SDAT VIN DNC AVDD VDD1 VDD2 VSS Pin Number 1 16 7 8 9 10 11 2 3 4 14 15 5 13 6,12 Crystal Output Clock Output Clock Output Clock Output Clock Output Clock Output Serial Interface (I2C) Clock Input Serial Interface (I2C) Data Analog Control Input for VCXO Do Not Connect. This pin should be left floating. Core and input Voltage Supply Voltage Supply for Outputs CLKC Voltage Supply for Outputs CLKD, CLKE, CLKF, CLKG Ground frequencies. Because the serial programming memory is volatile, the device will revert to its default configuration when power is cycled. Pin Description Crystal Input (27 MHz) or External Input Clock (27 MHz)
General Description
The CY24488 generates up to three independent clock frequencies, plus a buffered copy of the reference crystal frequency, from a single crystal or reference input. Five clock output pins are available, which allows some frequencies to be driven on two or more output pins. Outputs can also be individually enabled or disabled. When a CLK output is individually disabled, it drives low. The analog voltage controlled crystal oscillator (VCXO) allows teu e t "u"h rfrn ecytloaf q e c ta i h s ro p l te eee c rs t r u n y h ts l a e slightly higher or lower than nominal. Doing so will cause all output clocks to shift by an equivalent parts-per-million (PPM). The VCXO is controlled by the analog control voltage applied to the VIN pin. For applications that do not require the VCXO functionality, it can be disabled. A serial programming interface (SPI) permits in-system configuration of the device by writing to internal registers. It is used to set the output frequencies, enable and disable outputs, enable and disable the VCXO feature, etc. The SPI provides volatile programming. When powered down, the device reverts to its pre-SPI state. When the system is powered back up, the SPI registers will need to be configured again. Specific configuration details are given later in this data sheet. Customers may contact their Cypress FAE or salesperson for any frequency that is not listed in this data sheet. The data sheet can be updated with a new hex code for the requested frequency.
Reference Input
There are three programmable reference operating modes for the CY24488 family of devices. Table 2 shows the data values that must be programmed into the device for each of the reference operating modes. The correct values are required to ensure frequency accuracy and VCXO pullability. The first mode utilizes an external 27 MHz pullable crystal and incorporates the internal analog VCXO. The crystal is connected between the XIN/CLKIN and XOUT pins. See " rs l e u e ns frute d ti. C yt R q i me t o fr r eas a r " h l The second mode disables the VCXO input control and utilizes a standard 27 MHz crystal. Crystal requirements are relaxed relative to the VCXO mode. The crystal is connected between teXNC KNa dX U p s S e" rs l e u e ns h I/L I n O T i . e C yt R q i me t " n a r . In this mode, tie the VIN pin to AVDD. The third mode accepts an external 27 MHz reference clock, applied to the XIN/CLKIN pin. In this configuration, the XOUT pin must be unconnected. The VCXO feature is not available; tie the VIN pin to AVDD.
Analog VCXO
The VCXO feature allows the user to fine tune the output frequency via a control voltage applied to the VIN pin. A special pullable crystal must be used in order to have adequate VCXO pull range. This data sheet lists specific crystals that have been qualified for used with the CY24488. Specific serial programming values are also given for each crystal.
Default Start-up Configuration
The default state of the device refers to its state at power on. All output clocks are off except CLKG, which outputs a copy of the 27 MHz reference clock. The serial programming interface must be used to configure the device for the desired output
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CY24488
The special crystal requirements are eliminated if the VCXO feature is not needed. To disable the VCXO, the VIN pin must be tied high, and the appropriate register values given in the programming table must be programmed into the device. The VCXO is completely analog, so there is infinite resolution on the VCXO pull curve. The analog-to-digital converter steps that are normally associated with a digital VCXO input are not present in this device. VCXO Profile Figure 1 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset Figure 1. VCXO Profile
200 150 100
Tuning [ppm]
clock frequencies, as shown in the tables below. To do this, find the desired frequency from the appropriate table, then use the serial programming interface to write the specified hexadecimal data into the specified memory addresses. In some cases the data at a particular memory address controls multiple functions, so only some of the bit values are specified. Since a byte is the smallest unit of data that can be written, it is necessary to construct the full data byte prior to writing it. To do this, look in the other tables to find the correct values for the other bits in that byte. Any of the remaining output clocks (CLKF and CLKG) can be configured to generate duplicate copies of any the three primary clocks. Any of them can also drive a buffered version of the reference crystal frequency. Enabling and Disabling Output Clocks All output clocks can be individually enabled or disabled. Only CLKG is on at power on. All other clocks are off (driven low), and their respective PLLs are off. When using the serial programming interface to set an output to a desired frequency, the PLL Lock Time (AC Parameters Table) applies.
50 0 -50 -100 -150 -200 VCXO input [V] 0 0.5 1 1.5 2 2.5 3 3.5
When turning off an output, the output buffer and associated PLL are turned off by different register addresses. Therefore it is possible to turn off an output by programming just one byte, but the PLL will continue to run and consume some power. Therefore the PLL Lock Time does not apply when turning the output back on. The clock configuration tables also show a second off state that also turns off the PLL, saving additional power. This requires programming one or two additional bytes, and the PLL Lock Time applies. Output Drive Strength Output drive strength is configurable, with 2 bits available to s t e r e t n t fr a h up t h d fu v l i` ' e t di s e gh o e c o tu. e ea l a es1 , h vr T tu 0 which is medium-high. This is the recommended setting for outputs operating at 3.3V. The recommended setting for 2.5V o tus i ` ' w i mu tb po rmme b te u e. up t s 1 , h h 1 c s e rga d y h sr Table 10 shows which bits must be changed, and how to integrate these bits with other control bits to create valid bytes for shifting in. The user may program any output to a lower drive strength if E ia rb m. 0itel e t r e t n t, he1 ' MI po l ` ' h o sdi s e gh w i ` i s e 0s w vr l 1s the highest. Note that the lowest setting is very weak and is not suitable for most applications. Output Supply Voltage The clock outputs may be operated at either 3.3V or 2.5V. CLKC has its own power pin (VDD1), while all other clocks are powered by VDD2. VDD1 and VDD2 may be operated at different voltages if desired. AVDD must always be 3.3V. The CY24488 also has internal register settings that should be configured for the actual output supply voltage. The default settings are optimized for VDD1 = VDD2 = 3.3V. Table 10 and Table 3 show the values that need to be programmed for 2.5V supply voltage.
Crystal Requirements
The crystal requirements for the CY24488 differ for the VCXO and non-VCXO modes. In all cases, the device must be programmed correctly for the specific crystal used, as indicated in Table 2. Crystals for Non-VCXO Mode When not using the VCXO, the VIN pin should be tied high. The CY24488 uses a standard AT-cut parallel resonant crystal, which is available in a variety of packages. The key crystal parameter is load capacitance (CL). The CY24488 has programmable load capacitance, to match a range of crystal CL values. The specific configurations are shown in Table 2. Crystals with CL values outside this range are not recommended. Pullable Crystals for VCXO Mode When the VCXO mode is used, the crystal requirements increase considerably in order to ensure the pullable range and glitch-free pulling. Table 2 lists the crystals that Cypress has qualified for use with the CY24488, as well as the corresponding programming configurations. Customers wishing to use non-qualified crystals should first contact Cypress technical support.
Output Configurations
CLKC, CLKD, and CLKE are the three primary synthesized output clocks. For each one, the user can select from several
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Programming Flow
The device registers may be programmed in any sequence, but for convenience, a suggested programming flow is shown in Figure 2. Any step in this programming sequence may be skipped if the default value is the desired value. When programming an output frequency, the new frequency will be valid on that output after all of the specified data values have been written to all of the specified addresses. When changing an output frequency, the output may transition through one or more indeterminate frequencies between the writing of the first byte and the last byte. Note that some of the programming steps are not as independent as they appear in the flow diagram. In particular, addresses 48H, 53H, and 57H control both output frequencies and drive strength. Because a byte is the smallest unit that may be programmed through the serial interface, the user must consider both the frequency setting and the output drive strength when constructing the byte value to be written into these particular address. It is not necessary to write more than once to any given address, but that one write must have all of the bits set correctly.
Example: configure CLKC for 33.8688 MHz and 2.5V output. For address 48H, start with the value in Table 4: 89H (binary 10001001). Table 9 shows that bits 7 & 6 control the drive s e gh w i s o l b ` 'f m Table 10). Therefore, the t n t, h h h u e 1 (o r c d 1r final value is 11001001, which is C9H. This value is written once. Figure 2. Programming Flow
Default
CLKC, D & E Frequency settings (Tables 4 - 6)
Reference CLK & Crystal settings (Table 2)
CLKF & G Frequency settings (Tables 7 - 8)
Output Supply Voltage settings if 2.5V (Table 3)
Drive Strength settings for 2.5V or EMI (Tables 9, 4, 6, 8)
Table 2. Register Settings for VCXO and Reference Reference Clock and VCXO CLKIN (external reference), VCXO off Crystal, VCXO off Crystal, VCXO off Crystal, VCXO off (default) Crystal, VCXO off Crystal, VCXO on Crystal, VCXO on Crystal, VCXO on Crystal, VCXO on Crystal, VCXO on Crystal, VCXO on Crystal Manufacturer Part No. - any any any any KDS DSX530GA KDS DSX530GA RIVER FCX-03 KDK KDS Ecliptek ECX-6277 Package - any any any any 5x3.2 mm 5x3.2 mm 5x3.2 mm 5x3.2 mm SMD-49 SMD-49 Specified CL - 10.7 pF 12 pF 12.6 pF 14 pF 12.6 pF 10.7 pF 12 pF 12 pF 12 pF 12 pF 89 88 88 88 88 88 88 88 88 88 88 Address 16H 17H 3A 4F 5F 67 77 3A 2A 41 3A 39 41
Table 3. Register Settings for Output Supply Voltages Output CLKC CLKD, CLKE, CLKF, CLKG Output Supply Voltages VDD1 = 3.3V VDD1 = 2.5V VDD2 = 3.3V VDD2 = 2.5V Address 41H BF (default) 7F - - 43H - - A0 (default) 90
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CY24488
Table 4. CLKC Output Frequencies (Audio, iLink, or HDMI) Frequency (MHz) CLKC off and PLL off (default) CLKC off 25.175 28.322 6.144 (48K x 128) 12.288 (32K x 384) 16.384 (32K x 512) 18.432 (48K x 384) 24.576 (48K x 512) 36.864 (48K x 768) 11.2896 (44.1K x 256) 16.9344 (44.1K x 384) 22.5792 (44.1K x 512) 33.8688 (44.1K x 768) Application - - HDMI HDMI Audio Audio Audio Audio Audio, iLink Audio Audio Audio Audio Audio Frequency Error - - 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm Register Address 0AH - - 01 10 17 17 17 17 17 17 17 17 17 17 0BH - - 07 39 3E 3E 3E 3E 3E 3E 3E 3E 3E 3E 0CH 88 - D2 E2 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 0DH - - 26 94 1C 1C 19 1C 1C 1C 30 30 30 30 0EH - - 18 39 06 06 0E 06 06 06 16 16 16 16 0FH 44 - 72 6A 64 64 64 64 64 64 66 66 66 66 48H[1] 8D 8D AD 91 A5 A9 81 89 B5 95 A5 85 A9 89
Table 5. CLKD Output Frequencies (Video, Pixel rate, USB, modem or iLink) Frequency (MHz) CLKD off and PLL off (default) CLKD off 12 24 48 4.9152 11.0592 24.576 27 (reference) 27.027 54 (ref * 2) 54.054 74.25/1.001 74.25 81 (ref * 3) 148.5/1.001 148.5 Application - - USB USB USB Modem Modem iLink Video Video Video Video Video pixel rate Video pixel rate Video Video pixel rate Video pixel rate Frequency Error - - 0 ppm 0 ppm 0 ppm +38 ppm +11 ppm 6 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm Register Address 10H - - 01 07 07 18 39 56 - 7B 02 7B 59 00 00 59 00 11H - - 08 1E 1E 21 8F 8E - F2 0E F2 F8 03 07 F8 03 12H 00 - 30 30 30 26 28 33 02 33 30 33 2C 22 30 2C 22 50H 8E 8E A2 86 8A A2 A6 82 9A 86 8A 8A 96 96 B6 B2 B2
Note 1. Bt [:] o t l L Cdi s e gh T ev l s i ni titb c r s o dt adi s e ghs t go ` ' e Table 9 and Table 10. i 76 c nr C K r e t n t. h a e g e n h a l or p n o r e t n t et f 0 S e s o vr u v se e vr i n 1.
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CY24488
Table 6. CLKE Output Frequencies (Ethernet, Video, PCI, Processor) Frequency (MHz) CLKE off and PLL off (default) CLKE off 13.5 27 (reference) 54 81 108 20 25 30 33.333333 40 50 60 66.666666 80 100 Table 7. CLKF Output Clock Frequency (MHz) CLKF off (default) 27 MHz reference Copy of CLKC Copy of CLKD Copy of CLKE
\
Application - - Video Video Video Video Video Processor Ethernet Processor PCI Processor Processor Processor PCI Processor Processor
Frequency Error - - 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm 0 ppm
Register Address 13H - - 00 - 00 00 00 07 07 01 19 07 19 01 19 07 19 14H - - 05 - 06 07 06 26 17 08 62 26 62 08 62 26 62 15H 00 - 26 02 24 24 24 24 30 28 30 30 30 28 30 30 30 53H[2] 3E 3E 8E 6E 2E DE 5E 9E AE AE AE AE 2E DE DE DE 5E
Address 55H Data value (hex) 0C 18 copy of data from Table 4 address 48H copy of data from Table 5 address 50H copy of data from Table 6 address 53H, divided by 4[3]
Table 8. CLKG Output Clock (Default = Reference out) Frequency (MHz) CLKG off 27 MHz reference (default) Copy of CLKC Copy of CLKD Copy of CLKE Address 57H bits [7:6] 10 di s e gh(ea l 1 ) s eTable 10 r e t n t d fu = 0 - e vr t di s e gh(ea l 1 ) s eTable 10 r e t n t d fu = 0 - e vr t di s e gh(ea l 1 ) s eTable 10 r e t n t d fu = 0 - e vr t di s e gh(ea l 1 ) s eTable 10 r e t n t d fu = 0 - e vr t bits [5:0] 001100 011000 b s :] f d rs 4 H-s eTable 4 i[ 0 o a de s 8 t5 e b s :] f d rs 5 H-s eTable 5 i[ 0 o a de s 0 t5 e b s :] f d rs 5 H-s eTable 6 i[ 2 o a de s 3 t7 e
Notes 2. Bt [:] o t l L Ddi s e gh T ev l s i ni titb c r s o dt adi s e ghs t go ` ' e Table 9 and Table 10. i 10 c nr C K r e t n t. h a e g e n h a l or p n o r e t n t et f 0 S e s o vr u v se e vr i n 1. 3. Bt [:] f d rs 5 Haed n c r. id gb 4ie u a n t r h s in b 2b s i 76 o a de s 5 r o ' ae Dv i y s q i l to i t h t g y i. s t in ve g f i t
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CY24488
Table 9. Register Settings for Output Drive Strength[4] Output Clock CLKC CLKD CLKE CLKF CLKG Drive strength bits bits[7:6] of 48H bits[1:0] of 53H bits[7:6] of 54H bits[5:4] of 56H bits[7:6] of 57H 1 DS
[]
bit 7 DS DS
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 DS
bit 0
see address 48H in Table 4 see address 53H in Table 6 0 1 DS 0 0 0 0 0 0 0 0 0
see address 57H in Table 8
Table 10. Drive Strength (DS) Values[4] DS Value 00 01 10 (default) 11 Drive Strength Very low Medium low Medium high High 3.3V Output EMI Adjustment EMI Adjustment Standard Extra Drive 2.5V Output EMI Adjustment EMI Adjustment EMI Adjustment Standard
Notes 4. T e ea l r e t n t ( S s t g o a c css1 ' l up tp ci t n fr .Vo tus r g e frh v lue. Output specifications for 2.5V outputs h d fu di s e gh D ) et fr l l k i` . l tu s e i ai so 33 up tae i n o ti a tv r i n lo 0Ao fo c v s aeg e fr s t go ` ' oc a g teD s t g ,h s r l rga n i efc mu t eu e t po rm i ted s values. Users may program r i n o a et f 1 T h n e h S et s te ei po rmmi n r e s b s d o rga n h e i v i n 1. i n a g ta red i a y -i a e b t eti o tu s e i ai s in t ev l fr et g oh rh n` ' .V o ` '25 )S e DC Parameters and AC Parameters n n 2b v l , u c r n up t p ci t n wl o b ad o s t s te ta 1 ( 3 ) r1 (.V. e the tu a fo c l i i n 03 1 tables for further details.
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CY24488
Serial Programming Interface Protocol and Timing
The CY24488 utilizes pins SDAT and SCLK for a 2-wire serial interface that operates up to 400 kbit/s in Read or Write mode. The basic Write protocol is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4. Device Address The device address is a 7-bit value. The default serial interface address is 47H. Data Valid Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 5. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 6. START Sequence - Start Frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). STOP Sequence - Stop Frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop Frame frees the bus to write to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write Mode the CY24488 will respond with an Acknowledge (ACK) pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 7 (N = the number of bytes transmitted). During Read Mode the acknowledge pulse after the data packet is sent is generated by the master.
Writing Multiple Bytes In order to write more than one byte at a time, the master does not end the write sequence with a STOP condition. Instead, the master can send multiple contiguous bytes of data to be stored. After each byte, the slave responds with an acknowledge bit, the same as after the first byte, and will accept data until the acknowledge bit is responded to by the STOP condition. When receiving multiple bytes, the CY24488 internally increments the register address.
Read Operations
Read operations are initiated the same way as Write operat n e c p ta teRW b o tes v a de ss e t ` i s xe th th / i fh l e d rs is to 1 o t a ' (HIGH). There are three basic read operations: current address read, random read, and sequential read. Current Address Read The CY24488 has an onboard address counter that retains 1 more than the address of the last word access. If the last word w i no ra w sw r `, h n ac r n a de sra rt r e d a od n te t e ' ur t d rs e d e o eai w u rtr te a e trdno ai ` 1 Wh n p rt n o l eun h v l s e il t nn ' e o d uo c o +. the CY24488 receives the slave address with the R/W bit set t a`,h C 2 4 8i u sa a k o l g a dt n mi o 1 te Y 4 8 s e n cn we e n r s t ' s d a s the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY24488 to stop transmission. Random Read Through random read operations, the master may access any memory location. To perform this type of read operation, first set the word address. Send the address to the CY24488 as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next the master reissues the control b t wt te / b t s t `. h C 2 4 8 h ni u s n y i h RW y e t 1 T e Y 4 8 te s e a eh e o' s acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY24488 to stop transmission. Sequential Read Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmission of the first 8-bit data word. This action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master may serially read the entire contents of the slave device memory. Note that register addresses outside of 0AH to 17H and 40H to 57H can be read from but are not real registers and do not contain configuration information. When the internal address pointer points to the FFH register, after the next increment, the pointer will point to the 00H register.
Write Operations
Writing Individual Bytes A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (SDAT = 0/LOW). The next eight bits must contain the data word intended for storage. After the data word is received, the slave responds with another acknowledge bit (SDAT = 0/LOW), and the master must end the write sequence with a STOP condition.
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CY24488
Figure 3. Data Transfer Sequence on the Serial Bus SCL
SDAT
Address or Acknowledge Valid Data may be changed STOP Condition
START Condition
Figure 4. Data Frame Architecture
SDAT Write
Multiple Contiguous Registers
Start Signal
1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address
1 Bit Slave ACK
1 Bit Slave ACK 8-bit Register Data (XXH+1)
1 Bit Slave ACK 8-bit Register Data (XXH+2)
1 Bit Slave ACK 8-bit Register Data (FFH)
1 Bit Slave ACK
1 Bit Slave ACK
1 Bit Slave ACK
8-bit Register Address (XXH)
8-bit Register Data (XXH)
8-bit Register Data (00H) Stop Signal
SDAT Read
Current Address Read Start Signal
1 Bit 1 Bit Slave R/W = 1 ACK 7-bit Device Address
1 Bit Slave ACK
1 Bit Master ACK
8-bit Register Data Stop Signal
SDAT Read
Multiple Contiguous Registers
Start Signal
1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address
1 Bit Slave ACK
1 Bit Master ACK 8-bit Register Data (XXH)
1 Bit Master ACK 8-bit Register Data (XXH+1)
1 Bit Master ACK 8-bit Register Data (FFH)
1 Bit Master ACK
1 Bit Master ACK
1 Bit Master ACK
8-bit Register Address (XXH)
7-bit Device Address +R/W=1
8-bit Register Data (00H) Stop Signal
Repeated Start bit
Figure 5. Data Valid and Data Transition Periods
Data Valid Transition to next Bit
SDAT
tDH
tSU
CLKHIGH VIH
SCLK
VIL
CLKLOW
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CY24488
Serial Programming Interface Timing
Figure 6. Start and Stop Frame
SDAT
START
Transition to next Bit
SCLK
STOP
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDAT +
START DA6 DA5 DA0 R/W ACK RA7
+
RA6 RA1 RA0 ACK D7 D6
+
D1 D0 ACK STOP
+ SCLK
+
+
Serial Programming Interface Timing Specifications
Parameter fSCLK CLKLOW CLKHIGH tSU tDH Description Frequency of SCLK Start Mode Time from SDA LOW to SCL LOW SCLK LOW Period SCLK HIGH Period Data Transition to SCLK HIGH Data Hold (SCLK LOW to data transition) Rise Time of SCLK and SDAT Fall Time of SCLK and SDAT Stop Mode Time from SCLK HIGH to SDAT HIGH Stop Mode to Start Mode Min. - 0.6 1.3 0.6 100 0 - - 0.6 1.3 Max. 400 - - - - - 300 300 - - Unit kHz s s s ns ns ns ns s s
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Absolute Maximum Conditions
Parameter Description Condition Min. -. 05 Relative to VSS Non-Functional MIL-STD-883, Method 3015 V-0 @1/8 in. 16 TSSOP -. 05 -5 6 2000 - 1 Max. 4.6 Unit V AVDD/VDD1 Core Supply Voltage /VDD2 VIN TS ESDHBM UL-94 MSL Input Voltage Temperature, Storage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level
VDD + 0.5 VDC +125 - 10 C Volts ppm
Pullable Crystal Specifications (for VCXO applications)[5]
Parameter FNOM CLNOM R1 DL F3SEPHI[6] F3SEPLO
[6]
Description AT-cut Crystal Nominal Load Capacitance Equivalent Series Resistance (ESR) Crystal Drive Level
Comments Parallel resonance, Fundamental mode Order crystal at one specific CLNOM 0 ppm Fundamental mode (CL = Series) Nominal VDD @ 25C over 120 ppm Pull Range
Min. 11.4 - - 240 -
Typ. 27 12 - - - -
Max. 12.6 40 300 -
Unit MHz pF W ppm
Third Overtone Separation from 3*FNOM Mechanical Third (High side of 3*FNOM) Third Overtone Separation from 3*FNOM Mechanical Third (Low side of 3*FNOM)
- 2 ppm 10
Non-pullable Crystal Specifications (for non-VCXO applications)[5]
Parameter FNOM CLNOM R1 DL Description AT-cut Crystal Nominal Load Capacitance Equivalent Series Resistance (ESR) Crystal Drive Level Comments Parallel resonance, Fundamental mode Order crystal at one specific CLNOM 0 ppm Fundamental mode (CL = Series) Nominal VDD @ 25C 10.7 - - Min. Typ. 27 12 - - 14.0 40 300 Max. Unit MHz pF W
Recommended Operating Conditions
Parameter AVDD VDD1/VDD2 TA CLOAD tPU Core Operating Voltage Output Operating Voltage Ambient Temperature Maximum Load Capacitance Power up time for all VDDs reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 3.0 2.3 -0 1 - 0.05 Typ. 3.3 3.3 2.5 - - - Max. 3.6 3.6 2.7 70 15 500 Unit V V V C pF ms
Notes 5. Device operates to following specs which are guaranteed by design. 6. Increased tolerance available from pull range less than 120 PPM.
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DC Parameters [7]
Parameter IOH[8] IOL[8] IIH IIL VIH VIL VVCXO CIN IVDD CINXIN CINXTAL Description Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage VIN Input Range Input Capacitance Supply Current Input Capacitance at XIN/CLKIN XIN/CLKIN pin only VDD Current VCXO Disabled External Reference Conditions VOH = VDD -05 V = 3.3V ., DD VOL = 0.5, VDD = 3.3V VIH = VDD, excluding Vin, XIN/CLKIN VIL = 0V, excluding Vin, XIN/CLKIN XIN/CLKIN input CMOS levels XIN/CLKIN input CMOS levels Min. 12 12 - - 0.7xAVDD - 0 - - - - Typ. - - 5 5 - - - - 60 15 12 Max. - - 10 10 - 0.3xAVD
D
Unit mA mA A A V V V pF mA pF pF
AVDD TBD - - -
Input Capacitance at Crystal VCXO Disabled Fixed Freq. Oscillator
AC Parameters[7]
Parameter 1/t1 DC1
[8, 9]
Description Output Frequency Output Duty Cycle (excluding REFOUT Output Duty Cycle (excluding REFOUT
Conditions PLL minmax/Dividermaximum Duty Cycle is defined in Figure 9; t2/t1, 50% of VDD
External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz) External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz)
Min. 4.2 45
Typ. - 50
Max. Units 166 55 MHz %
DC2[8, 9]
Duty Cycle is defined in Figure 9; t2/t1, 50% of VDD Duty Cycle is defined in Figure 9; t2/t1, 50% of VDD (XIN/CLKIN Duty Cycle = 45/55%) Output Clock Edge Rate. Measured from 20% to 80% of VDD. CLOAD = 15 pF. See Figure 10. Output Clock Edge Rate. Measured from 80% to 20% of VDD. CLOAD = 15 pF See Figure 10. Period Jitter; VDD1 = VDD2 = 3.3V, drive strength = `' 1 0 From end of serial programming sequence to correct output frequency
40
50
60
%
DCREFOUT[8, 9] Output Duty Cycle ER[8] EF[8] T9 T10 f XO Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time
40 0.75 0.75 - - 110
50 1.2 1.2 250 1 120
60 - - - 5 - -
% V/ns V/ns ps ms ppm
VCXO Crystal Pull Range Using non-SMD-49 crystal specified in Table 2. Nominal Crystal Frequency Input assumed (0 ppm) @ 25C and 3.3V Using SMD-49 crystal specified in Table 2. Nominal Crystal Frequency Input assumed (0 ppm) @ 25C and 3.3V
105
120
ppm
Notes 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. 8. D i s e ghs t g : 0 fr .Vo tus ` ' r .Vo tus r e t n t et s ` ' 33 up t 1 f 25 up t vr i n 1o ;1o . 9. Guaranteed when values in Table 3 and Table 9 are programmed to match the output supply voltage.
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Test and Measurement Set-up
Figure 8. Test and Measurement Diagram
V DDs DUT 0.1 F
Outputs C LOAD
GND
Voltage and Timing Definitions
Figure 9. Duty Cycle Definition t1 t2 V DD 50% of V DD Clock O utput 0V
Figure 10. ER = (0.6 VDD)/t3, EF = (0.6 DD)/t4 V t3 t4
V DD 80% of V DD
Clock O utput
20% of V DD 0V
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Ordering Information
Part Number Lead-free CY24488ZXC CY24488ZXCT 16-pin TSSOP 16-pin TSSOP - Tape and Reel Commercial, 0C to +70C Commercial, 0C to +70C Type Production Flow
Package Drawing and Dimensions
Figure 11. 16-lead TSSOP 4.40 mm Body Z16.173
51-85091-*A
All product and company names mentioned in this document are trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY24488 Quad PLL Clock Generator with Serial Interface (I2C) (Final) Document Number: 001-09608 REV. ** *A ECN NO. 497098 504259 Issue Date See ECN See ECN Orig. of Change RGL RGL New data sheet Minor text additions Change status from Advance Information to Final Description of Change
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